VSC Training Course: Node-Level Performance Engineering, March 24-26, 2020

    Description:

    This course covers performance engineering approaches on the compute node level. Even application developers who are fluent in OpenMP and MPI often lack a good grasp of how much performance could at best be achieved by their code. This is because parallelism takes us only half the way to good performance. Even worse, slow serial code tends to scale very well, hiding the fact that resources are wasted. This course conveys the required knowledge to develop a thorough understanding of the interactions between software and hardware. This process must start at the core, socket, and node level, where the code gets executed that does the actual computational work. We introduce the basic architectural features and bottlenecks of modern processors and compute nodes. Pipelining, SIMD, superscalarity, caches, memory interfaces, ccNUMA, etc., are covered. A cornerstone of node-level performance analysis is the Roofline model, which is introduced in due detail and applied to various examples from computational science. We also show how simple software tools can be used to acquire knowledge about the system, run code in a reproducible way, and validate hypotheses about resource consumption. Finally, once the architectural requirements of a code are understood and correlated with performance measurements, the potential benefit of code changes can often be predicted, replacing hope-for-the-best optimizations by a scientific process.

    This course provides –via lectures, demos, and hands-on labs– scientific training in Computational Science, and in addition, the scientific exchange of the participants among themselves.

    This course is organized in cooperation with the Erlangen Regional Computing Center (RRZE).

    Agenda:

    First day:

    08:45 - 09:00   local registration
    09:00 - 13:00   lectures and hands-on labs (with breaks: 11:00-11:15)
    13:00 - 14:00   lunch break
    14:00 - 17:00   lectures and hands-on labs (with breaks: 15:15-15:30)

    Second day:

    09:00 - 13:00   lectures and hands-on labs (with breaks: 11:00-11:15)
    13:00 - 14:00   lunch break
    14:00 - 17:00   lectures and hands-on labs (with breaks: 15:15-15:30)

    Third day:

    09:00 - 13:00   lectures and hands-on labs (with breaks: 11:00-11:15)
    13:00 - 14:00   lunch break
    14:00 - 17:00   lectures and hands-on labs (with breaks: 15:15-15:30)

    Content:

    Introduction

    • Our approach to performance engineering
    • Basic architecture of multicore systems: threads, cores, caches, sockets, memory
    • The important role of system topology

    Tools topology & affinity in multicore environments

    • Overview
    • likwid-topology and likwid-pin

    Microbenchmarking for architectural exploration

    • Properties of data paths in the memory hierarchy
    • Bottlenecks
    • OpenMP barrier overhead

    Roofline model: basics

    • Model assumptions and construction
    • Simple examples
    • Limitations of the Roofline model

    Tools: hardware performance counters

    • Why hardware performance counters?
    • likwid-perfctr
    • Validating performance models

    Roofline case studies

    • Dense matrix-vector multiplication
    • Sparse matrix-vector multiplication
    • Jacobi (stencil) smoother

    Optimal use of parallel resources

    • Single Instruction Multiple Data (SIMD)
    • Cache-coherent Non-Uniform Memory Architecture (ccNUMA)
    • Simultaneous Multi-Threading (SMT)

    Extending Roofline: The ECM performance model

    Optional: Pattern-based performance engineering 

    Prerequisites:

    Participants should be able to work on the Linux command line, must have basic knowledge in programming with Fortran or C, and basic OpenMP.

    Lecturers:

    Georg Hager and Gerhard Wellein (RRZE / HPC, Uni. Erlangen)

    Language:

    English

    Date, Time, and Location:

    24. - 26.03.2020, 09:00 - 17:00,
    FH Internet-Raum FH1 (TU Wien, Wiedner Hauptstraße 8-10, ground floor, red area)

    Registration:

    Opens external link in new windowRegistration form

    Registration will start on January 21, 2020.

    Registration deadline is Tuesday, March 3, 2020, with priority rules. Acceptance will be approved on March 4, 2020. As long as seats are available there will be an extended registration period without priority rules.

    Priority for acceptance: first - active users of the VSC systems, second - students and members of Austrian universities and public research institutes, third - other applicants.

    Fee:

    VSC users: none
    Students and members of Austrian universities and public research institutes: none
    Students and members of other universities and public research institutes: 180 €
    Others: 600 €

    Information about payment will be provided with the confirmation email.

    Coffee breaks are included in the course fee (lunch is not included).

    Slides:

    A link to the presentation slides will be available at course start.

    Local Organizer / Contact:

    Claudia Blaas-Schenner, vsc-seminar@list.tuwien.ac.at

     

    Training events of VSC:

    Opens external link in new windowvsc.ac.at/training